The present invention relates to a semiconductor apparatus including a dynamic threshold field effect transistor (DTFET), and to a method of producing the same. More particularly, the present invention relates to a method of lowering the resistance of gate interconnections and concurrently making a high device packing density possible on semiconductor substrates.
Metal oxide semiconductor field effect transistor (MOSFET) devices have gained wide acceptance in the digital electronics industry. MOSFET devices are characterized by a threshold voltage required at the gate for the transistor to turn on or off and conduct or prevent the flow of current between the source and drain. The state of the MOSFET is therefore changed with the presence or absence of a minimum threshold voltage at the gate.
Recently, manufacturers and developers of integrated circuits have sought to improve performance by lowering the power supply voltages required by the transistors. However, as power supply voltages are scaled down, MOSFET threshold voltages cannot be lowered proportionately. The lowering of the threshold voltage is limited because a minimum threshold voltage has to be maintained, e.g. 200 mV, to ensure the circuits are not sensitive to noise, and the subthreshold leakage currents are not too high. As a result, device performance gain is not as desirable in technologies with low power supply voltages due to low gate-to-source overdrive, wherein the gate-to-source overdrive is proportional to the performance of the device and is defined as the gate-to-source voltage minus the threshold voltage.
One solution that has been proposed to alleviate the low overdrive problem is the dynamic threshold voltage FET (DTFET). In such systems, the threshold voltage dynamically adjusts as the gate input voltage changes. One method in which dynamic characteristics in the DTFET are achieved is by connecting the gate directly to the body of the FET as shown in FIG. 1. In the case of an N-type DTFET (i.e., a DTNFET), when the gate is low and the DTNFET is off, the threshold voltage is high providing good noise immunity and low leakage current. When the gate switches high to turn the DTNFET on, the threshold voltage is low (near zero) due to the negative body effect, i.e., forward bias voltage from source to body. Since the threshold voltage is low during most of the switching time, the DTNFET can have very good switching speed.
Unfortunately, limitations exist with the above described system. In particular, the use of DTFETs must be limited to silicon on insulator (SOI) technologies where the FET bodies are isolated. One disadvantage of the SOI DTFET is the high substrate resistance in the device body. In general, it is difficult to make good contact (uniformly low resistance) from gate to the body substrate. A typical scheme of an SOI NFET is shown in FIG. 2. (SOI PFET is similar except for the dopant types). The gate is connected to the body at one end. Since the body substrate resistance is very high, this scheme has the disadvantage that the device width has to be very narrow. In addition, the conventional contact can only reduce body resistance in one direction because the contact can only be made at the DTFET perimeter.
In addition, there is a challenge to develop a method of manufacturing DTFETs on the substrate such that the distance between body contacts is short enough so that the apparatus can take full advantage of DT-CMOS performance benefits. This can be illustrated as follows. The less stringent constraint requires that the body is at the gate voltage at the end of a system cycle such that Tb less than Tcycle, where Tb is the body RC time constant and Tcycle is the system cycle time. This less stringent constraint eliminates floating body history effects, but does not take full advantage of the DT-CMOS performance benefit. A more stringent constraint requires that the body voltage must be able to follow the gate voltage while a MOSFET switches to take full advantage of the DT-CMOS performance benefit such that Tb less than Tsw, where Tsw is a typical stage delay. The body RC time constant Tb can be expressed as Tbxcx9c(Rb/Leff)xc3x97(Csj+Cdj+Cgatexc3x97Leff)xc3x97(d/2)**2, where Rb is the body sheet resistance ranging between 2xcx9c10 kohm/square, Leff is the MOSFET channel length, Csj and Cdj are the drain and source junction capacitance to the body ranging between 0.5 and 1.5 fF/xcexcm, Cgate is the body capacitance to the MOSFET gate, and d is the distance between body contacts along the width of MOSFET gate. Cgate can be expressed as Cgatexcx9c3.5xc3x97(10 nm/Tox) fF/xcexcm, where Tox is the MOSFET effective gate oxide thickness. For a typical 1 GHz microprocessor where Tcyc equals 1 ns and Tsw equals 10xcx9c30 ps, the MOSFETs can have Leff as 0.08 xcexcm, Tox as 2.2 nm, Csj as 1 fF/xcexcm, Cdj as 1 fF/xcexcm and Rb as 6 kohm/sq. The less stringent constraint requires that d should be shorter than 4 xcexcm to eliminate history effects in a 1 GHz processor, while the more stringent constraint requires that d should be shorter than 0.4 xcexcm to take full advantage of DT-CMOS performance benefits.
Unfortunately, a conventional DT-CMOS gate-to-body contact adds about two lithographic minimum images to a MOSFET width to allow for alignment tolerances and adequate metal-strap contact areas. Therefore the distance between body contacts can be so large in a conventional DTFET apparatus that the apparatus cannot take full advantage of DT-CMOS performance benefits.
Therefore, without a method that allows high performance DTFETs to be implemented in SOI technologies with low gate interconnection resistance and high device packing density, the use of DTFETs will be greatly limited.
It is an advantage of the present invention to provide a method for reducing gate-to-body resistance to allow high performance of DTFET in SOI technologies.
It is a further advantage of this invention to provide a method for providing a high device packing density on a semiconductor substrate by forming a contact that uses less area than a conventional contact.
It is a further advantage of this invention to provide a method for making body contacts such that the distance between body contacts is short enough to allow a semiconductor device to take full advantage of DT-CMOS performance benefits.
It is still another advantage of this invention to reduce gate-to-body resistance in two directions of MOSFET width and to produce a contact within the gate.
The present invention generally provides a method of fabricating a FET comprising the steps of:
providing a substrate having a device area;
forming a gate on said substrate;
forming an electrically conductive contact structure from said gate to said device area, within said gate; and
forming diffusion regions in said device area having a channel therebetween.
The present invention also provides a semiconductor device comprising:
a substrate;
diffusion regions in said substrate having a channel therebetween; and
a gate on said substrate, wherein said gate includes a contact structure from said gate to said channel, within said gate.
The present invention further provides a semiconductor device comprising:
a substrate;
a source region and a drain region in said substrate having a channel therebetween;
a gate structure on a surface of the channel; and
a contact layer within said gate electrically connected to said channel.
The present invention also provides a method of fabricating a Field Effect Transistor (FET) comprising the steps of:
providing a substrate;
forming an insulator layer over the substrate;
forming a gate on the insulator layer over the substrate;
forming openings through the gate and the insulator layer down to the substrate;
disposing conductive material in the openings in electrical contact with the substrate;
forming a conductor layer over the gate and the conductive material in the openings to electrically connect the gate to the substrate at each of the openings; and
forming diffusion regions in the substrate having a channel therebetween.